Simplifying FPGA Complexity

Benefits of libraries

 

VHDL libraries are a powerful mechanism the language offers to collect common modules together for  reuse. Reuse is a key to success with FPGA design, it helps to design faster, easier and with verified and validated modules. Designing and testing a general purpose library is often considered as a time consuming effort and most often there is no time for FPGA designers to build a complete general purpose library.

Using our library allow designers to focus on high-level design without wasting time to develop building blocks.

 

Quality and support

 

Campera Electronic Systems meets  the highest standards

of quality and developed a rigorous design flow that dramatically reduce design flaws at each stage of the development process.

Customers with a valid support contract can benefit from our 24/7 support by mail and phone, all optional modules, testbenches and more.

 

Library Facts

 

Tested on Hardware

YES

 

Verification and Validation

Self checking testbench

Static Timing Analysis

Code Coverage

Linting

 

Supported FPGA

ANY

 

Supported Simulators

Aldec Active-HDL 9.1 or later

Riviera Pro 2014.02 or later

 

Supported Synthesizers

Mentor Precision r2013b.15 or later

Xilinx ISE 14.7/Vivado 2013.4 or later

Altera Quartus II v.14 or later

 

Deliverables

VHDL Source Code

Documentation

 

 

CES Utility Library

Datasheet

Each VHDL module in the Utility Library can be easily configured via generics, reset type (sync or async), reset level (active low or active high), output value on reset, memory depth and data width, to mention a few.

To allow for proper instantiation of hard core modules (such as Block Ram or DSP) a generic with vendor, synthesis tool and other specific information is propagated to each module.

 

Key Features

 

• vendor independent "off the shelf" VHDL cores for FPGAs (Xilinx, Altera, Achronix, Lattice and Microsemi) 

• VHDL modules are written in pure VHDL-93 standard (2008 available on demand), completely vendor independent

• optimized in terms of speed, power and resource usage

• architected, developed, verified, released and maintained through a rigorous and efficient process

• DO-254 and IEC-61508 compliance if required

 

Key Benefits

 

• No cost for hardware/tool version update/upgrade

• No time to re-generate the cores for different targets and/or tools

• Considerably faster simulations compared to vendor pre-synthesized IP Cores

• Configurable high quality VHDL modules available

• Customization available on demand

• More than 150 useful functions in the ces_util package

• More than 13.000 lines of VHDL source code and 7000 lines of comments

• CES internal VHDL coding standard to help you quickly understand the source code

• The ces_util_lib is the swiss army knife of every FPGA designer and is ideal for expert designers as well as beginners

• Ideal for Companies who start to work on FPGA design to start designing with a complete library of modules as well as expert designers

 

Applications

 

• All FPGA\CPLD design