Simplifying FPGA Complexity
Benefits of libraries
VHDL libraries are a powerful mechanism the language offers to collect common modules together for reuse. Reuse is a key to success with FPGA design, it helps to design faster, easier and with verified and validated modules. Designing and testing a general purpose library is often considered as a time consuming effort and most often there is no time for FPGA designers to build a complete general purpose library.
Using our library allow designers to focus on high-level design without wasting time to develop building blocks.
CES Utility Library
Campera-ES is on GitHub!
The company decided to release under MIT license its VHDL Utility Library
https://github.com/campera-es/ces_util_lib
More than 150 useful functions in the ces_util package
More than 13.000 lines of VHDL source code and
7000 lines of comments
The UTILITY LIBRARY is a collection of modules that are used in almost every FPGA design, it is the Swiss Army Knife of every FPGA designer. All the modules are vendor independent high quality VHDL code.
Campera Electronic Systems Srl designed and used these modules in all projects for over 8 years, they have been tested on more than 80 projects using Altera, Lattice, Microsemi and Xilinx FPGA/CPLD/SoC
In the UTILITY LIBRARY you will find a full set of memory modules (single port, dual port, true dual port), synchronous and asynchronous FIFOs, Encoders and Decoders and a lot of other essential modules.