Location: Livorno, Italy
Description: FPGA Designer for DSP Applications
Duration: 6 months
If you want to deal with a curricular or extra-curricular stage in a young, innovative, high-technology environment, if you want to study and work with state-of-the-art technology, CAMPERA will offer you the possibility to learn new methodology of FPGA design, to improve your knowledge in VHDL logic and DSP design on FPGAs.
The 6 months stage will introduce you to the latest improvements in VHDL-2008 and latest FPGA family, to our proprietary design flow and coding standard up to the design and verification of a middle size ASIP core, as we call our Application Specific IP Cores in VHDL 2008 for FPGAs. ASIPs are Intellectual Properties tailored for a specific application, as Radar/Sonar/Lidar, Radio-Astronomy, Biomedics and so on.
Your enthusiasm, analytical mind and knowledge will enable you to translate high-level requirements into a design-architecture with relevant specifications and develop it further into a working IP. You do this together with your colleagues. If you are flexible and you meet the following requirements: good knowledge of VHDL language and digital logic, understanding of Digital Signal Processing methods, experience with Xilinx Vivado\ISE or Altera Quartus II, good knowledge of the English language both oral and written, you can take into account to have a stage at CAMPERA Electronic Systems.
Pursuing Master of Science (MSEE) required
Knowledge of simulation, synthesis, and PAR software tools such as ModelSim, Xilinx ISE and/or Altera Quartus development tool sets;
Understanding of modern HW design;
FPGA (Altera or Xilinx) programming knowledge;
knowledge of laboratory debug techniques using digital scopes, logic analyzers and other complex measurement devices
How to Apply:
Send an email with your Curriculum Vitae by clicking on the "Apply" button above
Candidates are strongly encouraged to register on the Regione Toscana Giovanisi database for stage financing (