Setting generics/parameters for Synthesis

October 16, 2014

VHDL has the powerful feature of generics, while Verilog uses parameters for the same purpose. Both these techniques allow parameterisable designs, that is designs that can be easily re-used in different projects, with different parameters. This allow for design-resue, which is a key concept for today's HDL devlopment flow, to reduce costs and time to market and increase reliability and Quality of Results.

Here is an example of an entity declaration of a parameterised counter in VHDL:

 

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity counter is

  generic (

       nbits : natural;

       maxcount : natural

   );

  port (

      rst : in std_logic; 

     enable : in std_logic;

      clk : in std_logic;

      updown : in std_logic;

      count : out std_logic_vector(nbits-1 downto 0)

   );

end entity counter;

 

This can be simulated - the testbench instantiate the counter and sets the generic as follows

 

U1: entity work.counter

     generic map (

          nbits => 8,

          maxcount => 100)

     port map (

          rst => rst,

         enable => enable,

         clk => clk,

         updown => updown,

         count => count);

 

This works fine for simulation, but if you try to synthesize the above described counter on its own, the synthesis tool does not know the value of the generics. One solution to this is to simply assign the generics default values - the synthesis tool will then use those defaults values. If you do that, it makes sense to re-write the generic declaration so that each generic can be given a different default value.

Here is how: 

 

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity counter is

  generic (

       nbits : natural := 8;

       maxcount : natural := 255

   );

  port (

      rst : in std_logic;

      enable : in std_logic;

      clk : in std_logic;

      updown : in std_logic;

      count : out std_logic_vector(nbits-1 downto 0)

   );

end entity counter;



​Now you can synthesize the design without providing generics to the entity instantiation, in that case the default values would be used.

To go further than this, and override the generics from a synthesis tool, you can use tool specific features. Go back to the main FPGAs Developer's Guide and check the specific tool section to see how to override default generics.

 

Setting generics/parameters in Mentor Precision

 

Mentor Precision RTL can set generics from a Tcl command.

There is a deprecated option for the setup_design command, which is the -generics switch. The Tcl command has to set a "list of lists" as follows:

 

setup_design -generics { {nbits 4} {maxcount 10} }

 

The recommended way to set generics/parameters is to use the -overrides switch. Remember that VHDL generics are treated as case insensitive whereas Verilog parameters are treated as case-sensitive



setup_design -overrides { {nbits 4} {maxcount 10} }

 

Note the use of curly brackets to enclose each list. This command can be typed at the console of the Precision GUI, or included in a Tcl synthesis script.



Note that each tool has to analyze the code first to identify generics and/or parameters. It is recommended to put default values for generics/parameters so that the code will definitely synthesize even without overriding the generic values.

 

Setting generics/parameters in Altera Quartus II

 

Once you've loaded in your design, analyzes it by clicking the button Start Analysis and Synthesis.

Go to the menu option Assignments > Settings... and click on Default Parameters. You can now set the generics for your entity in the GUI.

 

Of course you can also use Tcl as we recommend, and include in your synthesis script the following lines 

 

  set_parameter -name nbits 4

  set_parameter -name maxcount 10

  

Setting generics/parameters in Xilinx ISE/Vivado

 

Xilinx Vivado



Once you've loaded in your design, set the generics by clicking the button Synthesis Settings.

Go to the menu option Synthesis Settings and click on More Options. You can now set the generics for your entity in the GUI (do not use white spaces inside the generic definition, as nbits = 4, type nbits=4 instead):

 

Of course you can also use Tcl as we recommend, and include in your synthesis script the following lines 

 

  synth_design -generic nbits=4

  synth_design -generic maxcount=10

  

Xilinx ISE



In Xilinx ISE, set up your project and import or edit your code.

To do this, carry out the following steps:

Right-click on Synthesize - XST and select Properties

Highlight the Category Synthesis Options in the left of the form

Set the Properties Display Level to Advanced, now you will be able to type in your generic/parameter settings.

The syntax is a space separate list of assignments such as nbits=4 maxcount=10.

In Xilinx Tcl, the following command has been created:

 

project set "Generics, Parameters" "nbits=4 maxcount=9" -process "Synthesize - XST"

 

Setting generics/parameters in Synopsys Synplify

 

Synopsys Synplify can set generics from a Tcl command or from the GUI.

Go to the menu Options > Configure VHDL Compiler. This menu has an Extract Generics button which will identify the generics and add them to the form, so you can fill in the values. 

 

You can still use the power of Tcl, again, as we recommend:

 

set_option -hdl_param -set nbits 4

set_option -hdl_param -set maxcount 10

 

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October 16, 2014

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