Setting generics/parameters for Synthesis

VHDL has the powerful feature of generics, while Verilog uses parameters for the same purpose. Both these techniques allow parameterisable designs, that is designs that can be easily re-used in different projects, with different parameters. This allow for design-resue, which is a key concept for today's HDL devlopment flow, to reduce costs and time to market and increase reliability and Quality of Results.

Here is an example of an entity declaration of a parameterised counter in VHDL:


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
  generic (

       nbits : natural;

       maxcount : natural

   );
  port (

      rst : in std_logic; 

     enable : in std_logic;

      clk : in std_logic;

      updown : in std_logic;

      count : out std_logic_vector(nbits-1 downto 0)

   );
end entity counter;

 

This can be simulated - the testbench instantiate the counter and sets the generic as follows
 

  U1: entity work.counter
     generic map (

          nbits => 8,

          maxcount => 100)
     port map (

          rst => rst,

         enable => enable,

         clk => clk,
         updown => updown,

         count => count);
 

This works fine for simulation, but if you try to synthesize the above described counter on its own, the synthesis tool does not know the value of the generics. One solution to this is to simply assign the generics default values - the synthesis tool will then use those defaults values. If you do that, it makes sense to re-write the generic declaration so that each generic can be given a different default value.

Here is how: 
 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
  generic (
       nbits : natural := 8;
       maxcount : natural := 255
   );
  port (
      rst : in std_logic;

      enable : in std_logic;
      clk : in std_logic;
      updown : in std_logic;
      count : out std_logic_vector(nbits-1 downto 0)
   );
end entity counter;



Now you can synthesize the design without providing generics to the entity instantiation, in that case the default values would be used.

To go further than this, and override the generics from a synthesis tool, you can use tool specific features. Go back to the main FPGAs Developer's Guide and check the specific tool section to see how to override default generics.