Scope of VHDL
VHDL is suited to the specification, design and description of digital electronic hardware.
VHDL is not ideally suited for abstract system-level simulation, prior to the hardware-software split. Simulation at this level is usually stochastic, and is concerned with modelling performance, throughput, queueing and statistical distributions. VHDL has been used in this area with some success, but is best suited to functional and not stochastic simulation.
VHDL is suitable for use today in the digital hardware design process, from specification through high-level functional simulation, manual design and logic synthesis down to gate-level simulation. VHDL tools usually provide an integrated design environment in this area.
VHDL is not suited for specialized implementation-level design verification tools such as analog simulation, switch level simulation and worst case timing simulation. VHDL can be used to simulate gate level fanout loading effects providing coding styles are adhered to and delay calculation tools are available. The standardization effort named VITAL (VHDL Initiative Toward ASIC Libraries) is active in this area, and is now bearing fruit in that simulation vendors have built-in VITAL support. More importantly, many ASIC vendors have VITAL-compliant libraries, though not all are allowing VITAL-based sign-off - not yet anyway.
In 1999, the IEEE approved Standard 1076.1, which is informally known as VHDL-AMS. It is a true super-set of VHDL, and includes analog and mixed-signal extensions.