Simplifying FPGA Complexity

What is an ASIP?

 

We call ASIP an Application Specific IP core. As well as an ASIC is a specialized integrated circuit, tailored to a specific application, an ASIP is an IP core tailored to a particular application, that could be easily integrated and used by the final user.

 

ASIP evaluation

 

Campera Electronic Systems works meets the highest standards of quality and developed a rigorous design flow that dramatically reduce design flaws at each stage of the development process.

The ASIP evaluation allows you to fully verify the ASIP capabilities:

· Simulation library for Aldec Simulators (Active-HDL v9.1 or higher and Riviera Pro v2014.02 or higher), other simulators on demand.

· Time-limited netlist to quickly evaluate resource utilization and timing closure and generates time-limited device programming files for in-hardware verification.

 

 

Quality and support

 

Campera Electronic Systems meets the highest standards

of quality  and developed a rigorous design flow that dramatically reduce design flaws at each stage of the development process.

We offer to all customers with a valid support contract all optional modules, test benches and more and 24/7 customer service and support by phone and by email.

 

Library Facts

 

Tested on Hardware

YES

 

Verification and Validation

Self checking testbench

Static Timing Analysis

Code Coverage

Linting

 

Supported FPGA

ANY

 

Supported Simulators

Aldec Active-HDL 9.1 or later

Riviera Pro 2014.02 or later

 

Supported Synthesizers

Mentor Precision r2013b.15 or later

Xilinx ISE 14.7/Vivado 2013.4 or later

Altera Quartus II v.14 or later

 

Deliverables

VHDL Source Code

Documentation

 

 

The Radar Processing ASIPs Cores are fully programmable DSP modules optimized for radar applications. RADAR ASIPs are fully parallel blocks, capable to process a huge amount of incoming data in real time. In the figure below are reported all the CES RADAR ASIPs available.

The Radar Processing Units are flexible, efficient, reliable and de-risked ways of building high performances Radar DSP processing Units on a FPGA.

 

Key Features

 

• vendor independent "off the shelf" VHDL cores for FPGAs (Xilinx, Altera, Achronix, Lattice and Microsemi) 

• VHDL modules are written in pure VHDL-93 standard (2008 available on demand), completely vendor independent

• optimized in terms of speed, power and resource usage

• architected, developed, verified, released and maintained through a rigorous and efficient process

• DO-254 and IEC-61508 compliance if required

• ASIP Cores can be supplied both in fixed point and in floating point (single or double precision) IEEE-Standard-754 compliant

 

Key Benefits

 

• No cost for hardware/tool version update/upgrade

• No time to re-generate the cores for different targets and/or tools

• Considerably faster simulations compared to vendor pre-synthesized IP Cores

• Configurable high performance VHDL modules available at no cost

• Customization available on demand

• More than 27.000 lines of VHDL source code and 4500 lines of comments

• CES internal VHDL coding standard to help you quickly understand the source code

 

 

Applications

 

• Radar/Lidar/Sonar

 

CES RADAR/SONAR Library