FAQ

Frequently asked questions and answers are listed below.

Contact

How can I contact Campera?

Safety critical applications

Can I use HDL code provided by Campera "as is" in my safety critical application?

VHDL's FAQ

What is the difference between VHDL and Verilog?

How must I write VHDL to make it synthesisable?

How many versions of VHDL are there?

Is VHDL going to be developed further?

A VHDL design can be moved to any tool or technology. Right?

Are there any tools to generate VHDL test benches automatically?

Can you give me a measure of the productivity improvements I should expect from VHDL?

I can see how to write abstract behavioural descriptions in VHDL, but how do you describe and simulate the actual hardware?

I've heard that VHDL is very inefficient for FPGAs. Is that true?

Are there any VHDL source code libraries available to save me having to re-invent common code fragments and functions?

Are freeware / shareware VHDL tools available?

Are there any inexpensive VHDL tools available?

What is Synthesis?

How about on-line information resources?

Verilog's FAQ

What is the difference between Verilog and VHDL?

What versions of Verilog are there?

Can I use Verilog for the analog part of a design?

How must I write Verilog to make it synthesisable?

A Verilog design can be moved to any tool or technology. Right?

I can see how to write abstract behavioural descriptions in Verilog, but how do you describe and simulate the actual hardware?

What is Synthesis?

How about on-line information resources?

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