The next level of test for your FPGAs

Traditional instruments used for FPGA's debug and test (Integrated Logic Analyzers) have fundamental limitations that make them useless and requires alternative debug methodologies (e.g. expensive external oscilloscopes). Most notably internal resources and memory are dedicated to debug purposes instead of more profitable functionalities.
Moreover those internal debug instruments and logic should be release and deployed in the final product, as the netlist under test contained those modules.

If your design already has an high speed interface (like GbE or USB) you could easily and more protifably use that I/O to debug and test your system, sending and retreiving data from an external PC for recording, analysis and playback.
Your internal resources will be free for functional purposes, long test vectors could be sent and captured from your board, using the PC memory.


  • Data rates are far superior than what you could obtain with a JTAG port, limited only by the channel bandwidth.
  • Acquisition memory limited only by the hard drives on your PC
  • Tests on target could be done sending test vectors used for RTL simulation on the target and capturing processed data (important for safety critical applications)

Our Test Suite comprises:

  • easily instantiable vendor independent HDL code (can be optimized for your target)
  • lightweight communication protocol (USB, GbE, ask for other interfaces)
  • PC drivers
  • GUI

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