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  • VHDL source files 

  • User manual​
  • Testbench
  • Reference design (Intel® Cyclone® 10 LP FPGA Evaluation Kit, can be easily adapted to any boards)

  • Two hours of support included

Site Based License Model

The license allows you to use the core in an unlimited number of projects originating within a 5-mile radius of an address designated as the "licensed site"


Supported FPGA

The MAC IP core has been tested and validate on Cyclone V, Cyclone 10, Stratix V, Spartan 6, Kintex Ultrascale+. The MAC uses a clock mux (to support triple speed) which is usually vendor and family dependent.

the STACK IP Core is pure VHDL, and it is supported on any FPGA 


Supported Simulators




Campera-ES Ethernet Solutions

Triple Speed Ethernet MAC

The Triple Speed Ethernet Media Access Controller (TSE MAC) is a generic triple speed 10/100/1000 Ethernet MAC suited for use in networking applications. In 1000 mode the TSE MAC can be connected with industry standard PHY devices using RGMII or GMII interface. When using 10/100 mode the TSE MAC uses the MII interface.

Key Features

  • Synthesizable, technology independent VHDL IP Core

  • IEEE 802.3-2008 compliant

  • Address filter

  • 10/100/1000 Media Access Controller

  • MII/GMII/RGMII interface

  • MDIO Interface

  • Automatic preamble generation and removal

  • 32-bit CRC generation/verification

  • Can be connected to any type of physical layer

  • Half Duplex collision check and retransmission

  • Payload padding and pad removal

  • Half/Full Duplex supported


The ces_comm_eth_stack is a generic Internet protocol stack designed to support 1Gbps-10Gbps throughputs on low-cost FPGAs.

Its goal is to achieve the highest theoretical throughput achievable for a given medium.

The following protocols are implemented in modular VHDL components:

  • TCP server/client (optional)

  • UDP

  • ARP

  • PING.

The code interfaces seamlessly with the CES_COMM_TSE_MAC Triple Speed Ethernet Media Access Controller. The MAC interface is generic and simple enough to interface with any Ethernet MAC component with minimum glue logic.


Key Features


  • Synthesizable, technology independent VHDL IP Core

  • IEEE 802.3

  • Ethernet packet encapsulation (RFC 894), IPv4

  • Up to 32 UDP TX/RX channels

  • Run time programmable IP addresses and Gateway, source and destination ports and MAC address

  • Supported protocols: IPv4 (no fragmentation), ARP (with Cache),  ICMP (Ping), UDP/IP Unicast and Multicast, TCP

  • The core is Ethernet MAC-independent but it seamlessly integrates with Campera-ES TSE MAC Core.

  • No external processor required



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