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  • VHDL source files 

  • User manual​
  • Testbench
  • Reference design (Xilinx VCU118 and Analog Devices AD9208 3Gsaps ADC)

  • Two hours of support included

Site Based License Model

The license allows you to use the core in an unlimited number of projects originating within a 5-mile radius of an address designated as the "licensed site"


Supported FPGA


The PFB Channelizer IP Core is pure VHDL, and it is supported on any FPGA.


Supported Simulators




Campera-ES Polyphase Filter Bank Channelizer

The polyphase filter must implement a Weigth-Overlap-Add (WOLA) operation on a serial data stream, s(i), multiplying segments of the stream by a filter function, f(i-i0), and then adding together individual frames of the result.

Input samples are presented in frames of nin consecutive samples, with the first sample marked by a sop (start of packet) pulse.

Due to clock speed limitations, samples are usually time multiplexed, i.e. <tmf> consecutive samples are presented together at each clock cycle. The same number of consecutive filtered samples are produced at the output.

The number of channels and the super sample rate factors ( the number of samples presented for each clock cycles) are limited only by the FPGA resources

Key Features

  • Configurable filter length and coefficient taps bit width

  • Configurable oversampling factor and overlapping length

  • Configurable Number of channels

  • Configurable input/output data width

  • Configurable time multiplexing factor for highly parallel operating architecture

  • Optimized algorithm for real-value input signals

  • Support interleaved input signals


  • Radio Astronomy

  • Radar\Sonar\Lidar

  • Communications Systems (SDR)

  • Wireless Communications

  • Electronic Warfare

  • Real-time spectral analysis

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