Automating tools flow with Tcl
Tcl/Tk scripting language has become the de-facto standard for EDA tools.
A good working knowledge of Tcl can dramatically help you gain greater productivity in using EDA tools for FPGA design. We recommend engineers to follow our main Tcl course, we use Tcl extensively in HDL courses as well.
Having a single common command language means that a designer only needs to learn Tcl in order to automate multiple tools. Furthermore, Tcl can also be used to coordinate and integrate different applications.
When Tcl is embedded in a design tool, the designer using the tool can write Tcl scripts to automate repetitive functions and extend the basic functions of the application. For example, a HDL designer using a Tcl-enabled simulation or synthesis tool (everyone in FPGA industry!) can write a Tcl script that runs a series of simulations or synthesis on a design, records data at key points, and presents the results to the user. This script can be saved for use as a regression test at later stage of the design.
Xilinx ISE - Vivado and Tcl
The example here shows how you can easily make a Tcl script for Xilinx ISE and Vivado.
Quartus II and Tcl
The example here shows how you can easily make a Tcl script for Altera Quartus II.