ASTRO VHDL LIBRARY 

High performance, vendor independent VHDL libray for Radioastronomy applications. Building your next channelizer or correlator on high end FPGAs has never been so quick and easy. 

IP Cores can be used also in Safety and Mission critical applications (EN 61508, DO 254, DO178).

All Campera's IP Cores are architected, designed and verified with a strict and rigorous development flow

 

Common characteristics to all IP cores from UTIL VHDL Library, configurable via generics

  • reset type (sync or async), reset level (active low or active high), output value on reset

 

The default values for the above generics (which means you don't have to explicitly map them if you don't need to change them)

  • Reset type = sync

  • Reset level = '1'

  • Output value on reset = 0

ASTRO IP Cores can be supplied both in fixed point and in floating point (single or double precision) IEEE-Standard-754 compliant

Each IP Core could be provided with a full documentation and Verification and Validation Procedure suitable for safety critical applications.

All CES IP Cores are delivered as netlist or encrypted source code for synthesis and RTL simulation.

Campera Electronic Systems developed a state of the art Channelizer im-plemented using Polyphase Filter Bank — FFT architecture. The polyphase filter uses a Weight-Overlap-Add (WOLA) operation on a serial data stream, multiplying segments of the stream by a filter function and adding together individual frames of the result. Oversampling and overlapping be-tween segments are implemented to extend alias free region. The following FFT stage is implemented using our high performance CES FFT Core.

Real Time bandwidth of up to 4.6 GHz, rejection out of band up to 63 dB and in band ripple 0.2 dB

Key Features

Configurable parameters

  • input/output data width

  • number of channels

  • time multiplexed input signals

  • 100% multiplier efficiency

  • Configurable filter taps

  • Configurable oversampling factor and overlapping length

  • Optimized algorithm for real-value input signals

  • configurable pipeline stages for maximum performances

  • reset type (synchronous or asynchronous),

  • reset level (active high, or active low)

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